1. Field of the Invention
The present invention relates to an output-buffer circuit of a through-rate-control type implemented on a semiconductor integrated circuit.
In recent years, a USB standard has been becoming increasingly popular as a communication standard for personal-computer peripherals. This standard defines a rising time Tr and a falling time Tf of an output signal. In order to meet the requirements for the rising time and the falling time, an output-buffer circuit of a through-rate-control type is generally used.
2. Description of the Related Art
FIG. 9 is a circuit diagram showing an example of a configuration of a related-art output-buffer circuit. FIG. 9 shows pad 1 serving as an output terminal, a driver circuit 2 for supplying an output signal OUT to the pad 1 in response to driver inputs PEN and NEN, and a bias circuit 3 for supplying voltages VP, VCNTR, and VN (VP&gt;VCNTR&gt;VN) to the driver circuit 2.
In the driver circuit 2, a pMOS transistor 4 has a source thereof connected to a VDD power line and a gate thereof receiving the voltage VP, and serves as a resistance. A pMOS transistor 5 has a source thereof connected to a drain of the pMOS transistor 4, a drain thereof connected to a node N1, and a gate thereof receiving the driver input NEN. A turned-on/off condition of the pMOS transistor 5 is controlled by the driver input NEN. The pMOS transistor 4 and the pMOS transistor 5 together form a pull-up circuit.
A nMOS transistor 6 has a drain thereof connected to the node N1 and a gate thereof receiving the driver input PEN, and is controlled by the driver input PEN with regard to a turned-on/off condition thereof. A nMOS transistor 7 has a drain thereof connected to the source of the nMOS transistor 6, a source thereof connected to a VSS power line, and a gate thereof receiving the voltage VN, and functions as a resistance. The nMOS transistor 6 and the nMOS transistor 7 together form a pull-down circuit.
An operational amplifier 8 has a non-inverted-input node receiving a voltage at the node N1 and an inverted-input node receiving the voltage VCNTR. The driver input PEN controls whether the operational amplifier 8 is activated. When the driver input PEN is at a HIGH level, the operation amplifier 8 is activated. When the driver input PEN is at a LOW level, on the other hand, the operation amplifier 8 is deactivated.
An operational amplifier 9 has a non-inverted-input node receiving the voltage at the node N1 and an inverted-input node receiving the voltage VCNTR. The driver input NEN controls whether the operation amplifier 9 is activated. When the driver input NEN is at the HIGH level, the operation amplifier 9 is deactivated. When the driver input NEN is at the LOW level, on the other hand, the operation amplifier 9 is activated.
A pMOS transistor 10 has a source thereof connected to the VDD power line, a gate thereof connected to an output terminal of the operational amplifier 8, and a drain thereof connected to the pad 1. The pMOS transistor 10 is used as an output transistor for a pulling-up purpose.
A nMOS transistor 11 has a drain thereof connected to pad 1, a gate thereof connected to an output terminal of the operational amplifier 9, and a source thereof connected to the VSS power line. The nMOS transistor 11 is used as an output transistor for a pulling-down purpose.
A pMOS transistor 12 has a source thereof connected to the VDD power line, a drain thereof connected to the gate of the pMOS transistor 10, and a gate thereof receiving the driver input PEN. A turned-on/off condition of the pMOS transistor 12 is controlled by the driver input PEN.
A nMOS transistor 13 has a drain thereof connected to the gate of the nMOS transistor 11, a source thereof connected to the VSS power line, and a gate thereof receiving the driver input NEN. The driver input NEN controls the turned-on/off condition of the nMOS transistor 13.
In this configuration, the PMOS transistors 4, 5, and 12, the nMOS transistors 6, 7, and 13, and the operational amplifiers 8 and 9 together form an output-transistor-control circuit.
A capacitor 14 is used for controlling a through-rate of the output signal OUT, i.e., used for controlling a rising time Tr and a falling time Tf. Here, the rising time Tr is defined as a time period necessary for the output signal OUT to rise from 10% to 90% of a maximum voltage thereof, and the falling time Tf is defined as a time period necessary for the output signal OUT to fall from 90% to 10% of a maximum voltage thereof.
In the bias circuit 3, a pMOS transistor 15 has a source thereof connected to the VDD power line and a gate thereof connected to a drain thereof, and the drain is connected to the gate of the pMOS transistor 4. A nMOS transistor 16 has a gate thereof connected to a drain thereof, which is in turn connected to the gate of the nMOS transistor 7, and further has a source thereof connected to the VSS power line.
A resistor 17 and a resistor 18 are connected in series between the drain of the pMOS transistor 15 and the drain of the nMOS transistor 16. A joint point between the resistor 17 and the resistor 18 is connected to the inverted-input nodes of the operational amplifiers 8 and 9.
In the bias circuit 3, the PMOS transistor 15, the resistors 17 and 18, and the nMOS transistor 16 serve as potential-divider elements. The voltage VP is generated at the drain of the pMOS transistor 15, and the voltage VCNTR is generated at the joint point between the resistor 17 and the resistor 18. Further, the drain of the nMOS transistor 16 has the voltage VN generated thereat.
In the output-buffer circuit having a configuration as described above, the pMOS transistor 5 and the nMOS transistor 6 are turned off and on, respectively, when both of the driver inputs PEN and NEN are HIGH as shown in FIG. 10. In this case, the voltage at the node N1 becomes LOW.
Also, the pMOS transistor 12 is turned off, and the operational amplifier 8 is activated so that the operational amplifier 8 supplies an output PDRV that is LOW. This turns on the pMOS transistor 10. Further, the operational amplifier 9 is deactivated, and the nMOS transistor 13 is turned on, so that the nMOS transistor 11 is turned off. The output signal OUT is thus at the HIGH level.
If the capacitor 14 was not provided, the output signal OUT would rise immediately when the PMOS transistor 10 is turned on. Because of presence of the capacitor 14, however, the rising time Tr of the output signal OUT becomes longer as the capacitor 14 initially holds electric charge.
This will be described in terms of a flow of an electric current. When both the driver input PEN and the driver input NEN are HIGH, a current Ip1 is generated via discharging of the non-inverted-input node of the operational amplifier 8, and a current Ic1 is generated by charge supplied from the capacitor 14.
The current Ip1 and the current Ic1 flow into the VSS power line via the nMOS transistors 6 and 7.
The amount of current In2 that can flow through the nMOS transistors 6 and 7 is limited by the turned-on resistance of the nMOS transistor 7, i.e., limited by the voltage VN. Because of this, only a limited amount of a current, which is less than a current Ifb1 combining the current Ip1 and the current Ic1, can flow through the nMOS transistors 6 and 7 to the VSS power line. As a result, the non-inverted-input node of the operational amplifier 8 does not exhibit a rapid voltage drop, so that the pMOS transistor 10 is turned on gradually. This elongates the rising time Tr of the output signal OUT.
In this manner, the rising time Tr of the output signal OUT of the output-buffer circuit can be adjusted by controlling the voltage VN which is applied to the gate of the nMOS transistor 7. The control of the voltage VN can be effected by changing the resistances of the resistors 17 and 18 in the bias circuit 3.
When both the driver input PEN and the driver input NEN are LOW, as shown in FIG. 11, the pMOS transistor 5 and the nMOS transistor 6 are turned on and off, respectively, so that the voltage at the node N1 becomes HIGH.
Also, the pMOS transistor 12 is turned on, and the operational amplifier 8 is deactivated, so that the pMOS transistor 10 is turned off. Further, the operational amplifier 9 is activated so that an output NDRV of the operational amplifier 9 becomes HIGH. Since the nMOS transistor 13 is turned off, the nMOS transistor 11 is turned on. In this case, therefore, the output signal OUT is at the LOW level.
If the capacitor 14 was not provided, the output signal OUT would fall immediately when the NMOS transistor 11 is turned on. Because of presence of the capacitor 14, however, the falling time Tf of the output signal OUT becomes longer as electric charge is supplied from the capacitor 14.
This will be described in terms of a flow of an electric current. When both the driver input PEN and the driver input NEN are LOW, a current In1 is generated by charge supplied to the non-inverted-input node of the operational amplifier 9, and a current Ic2 is generated by charge supplied to the capacitor 14. The current In1 and the current Ic2 flow through the pMOS transistors 4 and 5.
The amount of current Ip2 that can flow through the pMOS transistors 4 and 5 is limited by the turned-on resistance of the PMOS transistor 4, i.e., limited by the voltage VP. Because of this, only a limited amount of a current, which is less than a current Ifb2 combining the current In1 and the current Ic2, can flow through the PMOS transistors 4 and 5 from the VDD power line. As a result, the non-inverted-input node of the operational amplifier 9 does not exhibit a rapid voltage rise, so that the nMOS transistor 11 is turned on gradually. This elongates the falling time Tf of the output signal OUT.
In this manner, the falling time Tf of the output signal OUT of the output-buffer circuit can be adjusted by controlling the voltage VP which is applied to the gate of the pMOS transistor 4. The control of the voltage VP can be effected by changing the resistances of the resistors 17 and 18 in the bias circuit 3.
When the driver input PEN is LOW and the driver input NEN is HIGH (not shown), the operational amplifier 8 is deactivated, and the pMOS transistor 12 is turned on, so that the pMOS transistor 10 is turned off. Further, the operational amplifier 9 is deactivated, and the nMOS transistor 13 is turned on, so that the nMOS transistor 11 is turned off. In this case, the output is put in a high-impedance state.
In the related-art output-buffer circuit as shown in FIG. 9, the voltage VCNTR supplied to the inverted-input node of the operational amplifiers 8 and 9 is dependent on the resistance of the resistor 17 and the resistor 18. In order to secure stable operations of the operational amplifiers 8 and 9 and insure stability of the output operations, the resistance of the resistor 17 and the resistance of the resistor 18 must be identical. If the resistances of the resistor 17 and the resistor 18 vary due to inconsistent manufacturing processes, stable operations cannot be insured for the operational amplifiers 8 and 9, resulting in insufficient stability of output operations. Under some conditions of temperature, power voltages, etc., the rising time Tr and the falling time Tf of the output signal OUT may stray from the range defined by the USB standard.
Use of the operational amplifiers 8 and 9 helps to insure reliable operations of the pMOS transistor 10 and the nMOS transistor 11 forming an output-transistor pair even when the current Ip1 and In1 are small. Use of two operational amplifiers 8 and 9, however, results in an increased number of circuit elements, which acts against a cost reduction. Also, amplification operations of the operational amplifiers 8 and 9 makes it difficult to adjust a through-rate.
Accordingly, there is a need for an output-buffer circuit of a through-rate-control type which can insure stable output operations even under the presence of manufacturing-process variations, and can be implemented by a decreased number of circuit elements to facilitate a cost reduction.
Further, there is a need for an output-buffer circuit of a through-rate-control type which can insure stable output operations even under the presence of manufacturing-process variations, and can be implemented by a decreased number of circuit elements to facilitate a cost reduction while allowing an easy adjustment to be made to a through rate.